The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 05, 2018

Filed:

Aug. 31, 2016
Applicant:

Winbond Electronics Corp., Taichung, TW;

Inventor:

Yu-Ming Chen, Taichung, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 25/065 (2006.01); H01L 23/00 (2006.01); H01L 21/56 (2006.01); H01L 25/10 (2006.01); H01L 25/00 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 21/563 (2013.01); H01L 24/05 (2013.01); H01L 24/09 (2013.01); H01L 24/17 (2013.01); H01L 24/27 (2013.01); H01L 24/29 (2013.01); H01L 25/105 (2013.01); H01L 25/50 (2013.01); H01L 2224/0401 (2013.01); H01L 2225/06551 (2013.01); H01L 2225/06562 (2013.01);
Abstract

A packaging process of a semiconductor device includes following steps. A patterned conductive layer and a solder resist layer that covers the patterned conductive layer are formed through 3D-printing over a carrier having a cavity. The patterned conductive layer and the solder resist layer extend to the outside of the cavity from the inside of the cavity. One portion of the patterned conductive layer is exposed by the solder resist layer. At least one semiconductor device is mounted on the patterned conductive layer in the cavity, such that the at least one semiconductor device is electrically connected to the patterned conductive layer.


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