The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 05, 2018
Filed:
Dec. 18, 2015
Intel Corporation, Santa Clara, CA (US);
Russell S. Aoki, Tacoma, WA (US);
Michael R. Hui, Tacoma, WA (US);
Jonathon R. Carstens, Lacey, WA (US);
Michael S. Brazel, Federal Way, WA (US);
Daniel P. Carter, Olympia, WA (US);
Thomas A. Boyd, North Plains, OR (US);
Shelby A. Ferguson, Lacey, WA (US);
Rashelle Yee, Puyallup, WA (US);
Joseph J. Jasniewski, Olympia, WA (US);
Harvey R. Kofstad, Vernonia, OR (US);
Anthony P. Valpiani, Olympia, WA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Embodiments of the present disclosure describe package alignment frames for a local reflow process to attach a semiconductor package to an interposer. The frame may comprise a two frame system. The interposer may be on a mounting table or on a circuit board. The frame may include a body with a rectangular opening dimensioned to receive a semiconductor package to be coupled to the interposer. The frame may be to align a ball grid array of the semiconductor package with pads of the interposer. A second frame may be to receive the first frame and may be to align a ball grid array of the interposer with pads of the circuit board. A single frame may be used to couple a semiconductor package to an interposer and to couple the interposer to a circuit board. Other embodiments may be described and/or claimed.