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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9991208 B1

PDFFull Text
Date of Patent:
Jun. 05, 2018

Filed:

Sep. 09, 2016

Susceptor for holding a semiconductor wafer having an orientation notch, a method for depositing a layer on a semiconductor wafer, and semiconductor wafer

Applicant:

Siltronic Ag, Munich, DE;

Inventors:

Reinhard Schauer, Laufen, DE;

Christian Hager, Kastl, DE;

Assignee:

SILTRONIC AG, Munich, DE;

Attorney:

Brooks Kushman P.C.

Primary Examiner:

Jarrett Stark

Int. Cl.
CPC ...
C23C 16/00 (2006.01); H01L 23/544 (2006.01); H01L 21/02 (2006.01); H01L 21/68 (2006.01); H01L 21/687 (2006.01); H01L 29/16 (2006.01); C23C 16/24 (2006.01); C30B 25/12 (2006.01); C23C 16/458 (2006.01); C30B 25/20 (2006.01); C30B 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 23/544 (2013.01); C23C 16/24 (2013.01); C23C 16/4585 (2013.01); C30B 25/12 (2013.01); C30B 25/20 (2013.01); C30B 29/06 (2013.01); H01L 21/02381 (2013.01); H01L 21/02428 (2013.01); H01L 21/02532 (2013.01); H01L 21/02634 (2013.01); H01L 21/68 (2013.01); H01L 21/68735 (2013.01); H01L 21/68785 (2013.01); H01L 29/16 (2013.01); H01L 2223/54426 (2013.01); H01L 2223/54493 (2013.01);
Abstract

A semiconductor wafer processing susceptor for holding a wafer having an orientation notch during deposition of a layer on the wafer, having a placement surface for supporting the semiconductor wafer in the rear edge region of the wafer, the placement surface having a stepped outer delimitation, and an indentation of the outer delimitation of the placement surface for placement of the partial region of the edge region of the rear side of the wafer in which the orientation notch is located onto a partial region of the placement surface delimited by the indentation of the outer delimitation of the placement surface. The susceptor is used in a method for depositing a layer on a wafer having an orientation notch, and wafers made of monocrystalline silicon upon which layers are deposited using the susceptor have greater local flatness on both front and rear sides proximate the orientation notch.

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