The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 05, 2018

Filed:

Sep. 14, 2016
Applicant:

Hitachi Kokusai Electric Inc., Toyama-shi, JP;

Inventors:

Naofumi Ohashi, Toyama, JP;

Kazuyuki Toyoda, Toyama, JP;

Satoshi Shimamoto, Toyama, JP;

Toshiyuki Kikuchi, Toyama, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/302 (2006.01); H01L 21/461 (2006.01); H01L 21/66 (2006.01); H01L 21/3213 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 22/26 (2013.01); H01L 21/32136 (2013.01); H01L 21/7684 (2013.01);
Abstract

Provided is a technique capable of obtaining a satisfactory yield for a semiconductor device with an air gap. The technique includes a method of manufacturing a semiconductor device, including: (a) receiving a thickness information of a wiring layer formed on a substrate including: a first interlayer insulation film; and the wiring layer disposed on the first interlayer insulation film, the wiring layer including: copper-containing films used as wiring; and an inter-wiring insulation film having trenches filled with the copper-containing films and insulating the copper-containing films; (b) placing the substrate on a substrate support installed in a process chamber; and (c) etching the wiring layer using an etching gas based on an etching control value corresponding to the thickness information of the wiring layer.


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