The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 05, 2018

Filed:

Jul. 12, 2016
Applicant:

Samsung Electronics Co., Ltd., Suwon-Si, Gyeonggi-Do, KR;

Inventors:

Ji-Sang Lee, Iksan-Si, KR;

Sang-Soo Park, Hwaseong-Si, KR;

Dong-Kyo Shim, Seoul, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Suwon-si, Gyeonggi-Do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/12 (2006.01); G11C 7/10 (2006.01); G11C 7/12 (2006.01); G11C 7/14 (2006.01); G11C 7/22 (2006.01); G11C 8/10 (2006.01); G11C 29/56 (2006.01); G11C 11/56 (2006.01); G11C 29/42 (2006.01); G11C 29/52 (2006.01); G11C 16/04 (2006.01); G11C 16/26 (2006.01); G11C 29/50 (2006.01); G11C 29/04 (2006.01); G11C 27/02 (2006.01);
U.S. Cl.
CPC ...
G11C 29/1201 (2013.01); G11C 7/106 (2013.01); G11C 7/1006 (2013.01); G11C 7/1039 (2013.01); G11C 7/1057 (2013.01); G11C 7/12 (2013.01); G11C 7/14 (2013.01); G11C 7/222 (2013.01); G11C 8/10 (2013.01); G11C 11/5642 (2013.01); G11C 16/0483 (2013.01); G11C 16/26 (2013.01); G11C 29/42 (2013.01); G11C 29/50012 (2013.01); G11C 29/52 (2013.01); G11C 29/56008 (2013.01); G11C 27/02 (2013.01); G11C 2029/0411 (2013.01); G11C 2029/5004 (2013.01); G11C 2211/5642 (2013.01);
Abstract

A nonvolatile memory device with a memory cell array including a plurality of memory cells coupled to first through M-th wordlines and first through N-th bitlines (M>2, N>2), and a page buffer circuit including first through N-th page buffers that are coupled to the first through N-th bitlines, respectively, and generate first through N-th output data, respectively. A K-th page buffer includes first through L-th latches which generate read data by sampling a voltage of a K-th output line, which is discharged through a K-th bitline, at different sampling timings after a read voltage is applied to a P-th wordline (K≤N, L>1, P≤M). The K-th page buffer outputs the first output data if an error in the read data of the first latch is correctable.


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