The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 05, 2018
Filed:
Sep. 30, 2016
Cadence Design Systems, Inc., San Jose, CA (US);
Regis Colwell, Gibsonia, PA (US);
Patrick Hyde, Austin, TX (US);
Akshat Shah, Alexandria, VA (US);
Jeremiah Cessna, Pittsburgh, PA (US);
Timothy Rosek, Gibsonia, PA (US);
Khaled Elgalaind, Pittsburgh, PA (US);
CADENCE DESIGN SYSTEMS, INC., San Jose, CA (US);
Abstract
A method for placing and routing devices in a circuit layout is provided. The method includes determining devices to be placed in a circuit layout and a relative position of two devices in the circuit layout. In some embodiments, the method includes pre-routing channels in the circuit layout, determining routing trunk information from the pre-routed channels, and placing the two devices in the circuit layout based on the routing trunk information. Further, the method includes forming a first routing trunk along channels in the circuit layout, coupling the first routing trunk to one device of the two devices, and checking that a placement of a plurality of devices and the coupling the first routing trunk to one device of the plurality of devices meet a circuit layout specification. A computer system and a non-transitory computer-readable medium storing commands to execute the above method are also provided.