The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 05, 2018

Filed:

Dec. 21, 2011
Applicants:

Shlomo Raikin, Ofer, IL;

Raanan Sade, Kibutz Sanid, IL;

Robert Valentine, Kiryat Tivon, IL;

Julius Yuli Mandelblat, Haifa, IL;

Ron Shalev, Ceaseria, IL;

Larisa Novakovsky, Haifa, IL;

Inventors:

Shlomo Raikin, Ofer, IL;

Raanan Sade, Kibutz Sanid, IL;

Robert Valentine, Kiryat Tivon, IL;

Julius Yuli Mandelblat, Haifa, IL;

Ron Shalev, Ceaseria, IL;

Larisa Novakovsky, Haifa, IL;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/38 (2006.01); G06T 1/20 (2006.01); G06F 12/0811 (2016.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 13/16 (2006.01); G06T 1/60 (2006.01); G09G 5/00 (2006.01); G06F 12/0866 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0811 (2013.01); G06F 9/30043 (2013.01); G06F 9/30047 (2013.01); G06F 9/30087 (2013.01); G06F 9/3881 (2013.01); G06F 13/1673 (2013.01); G06F 13/38 (2013.01); G06T 1/20 (2013.01); G06T 1/60 (2013.01); G06F 12/0866 (2013.01); G09G 5/006 (2013.01);
Abstract

An apparatus and method are described for efficiently transferring data from a core of a central processing unit (CPU) to a graphics processing unit (GPU). For example, one embodiment of a method comprises: writing data to a buffer within the core of the CPU until a designated amount of data has been written; upon detecting that the designated amount of data has been written, responsively generating an eviction cycle, the eviction cycle causing the data to be transferred from the buffer to a cache accessible by both the core and the GPU; setting an indication to indicate to the GPU that data is available in the cache; and upon the GPU detecting the indication, providing the data to the GPU from the cache upon receipt of a read signal from the GPU.


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