The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 05, 2018

Filed:

Sep. 18, 2014
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Bang-Chiang Lan, Taipei, TW;

Li-Hsun Ho, Hsinchu County, TW;

Wei-Cheng Wu, Hsinchu County, TW;

Hui-Min Wu, Hsinchu County, TW;

Min Chen, New Taipei, TW;

Tzung-I Su, Yun-Lin County, TW;

Chien-Hsin Huang, Taichung, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); B81C 1/00 (2006.01); H01L 27/06 (2006.01);
U.S. Cl.
CPC ...
B81C 1/00246 (2013.01); B81C 1/00801 (2013.01); B81C 2201/014 (2013.01); B81C 2203/0714 (2013.01); B81C 2203/0742 (2013.01); B81C 2203/0792 (2013.01); H01L 27/0688 (2013.01);
Abstract

A method of fabricating an integrated structure for MEMS device and semiconductor device comprises steps of: providing a substrate having a transistor thereon in a semiconductor device region and a first MEMS component thereon in a MEMS region; performing a interconnect process on the substrate in the semiconductor device region to form a plurality of first dielectric layers, at least a conductive plug and at least a conductive layer in the first dielectric layers; forming a plurality of second dielectric layers and an etch stopping device in the second dielectric layers on the substrate in a etch stopping device region; forming a plurality of third dielectric layers and at least a second MEMS component in the third dielectric layers on the substrate in the MEMS region; and performing an etching process to remove the third dielectric layers in the MEMS region.


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