The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 29, 2018

Filed:

May. 22, 2017
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Chia-Lin Lu, Taoyuan, TW;

Chun-Lung Chen, Tainan, TW;

Kun-Yuan Liao, Hsin-Chu, TW;

Feng-Yi Chang, Tainan, TW;

Chih-Sen Huang, Tainan, TW;

Ching-Wen Hung, Tainan, TW;

Wei-Hao Huang, New Taipei, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 21/311 (2006.01); H01L 21/3115 (2006.01); H01L 21/768 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/78 (2013.01); H01L 21/31144 (2013.01); H01L 21/76897 (2013.01); H01L 21/3115 (2013.01); H01L 21/31155 (2013.01); H01L 21/76825 (2013.01); H01L 29/66545 (2013.01);
Abstract

A method for fabricating semiconductor device includes the steps of: providing a substrate having at least a gate structure thereon and an interlayer dielectric (ILD) layer surrounding the gate structure, wherein the gate structure comprises a hard mask thereon; forming a dielectric layer on the gate structure and the ILD layer; removing part of the dielectric layer to expose the hard mask and the ILD layer; and performing a surface treatment to form a doped region in the hard mask and the ILD layer.


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