The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 29, 2018

Filed:

Sep. 15, 2016
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Jeffrey Junhao Xu, San Diego, CA (US);

Mustafa Badaroglu, Kessel-Lo, BE;

Da Yang, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); H01L 27/00 (2006.01); H01L 27/02 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0207 (2013.01); G06F 17/5068 (2013.01); G06F 17/5072 (2013.01); G06F 17/5077 (2013.01); H01L 29/4232 (2013.01);
Abstract

Minimum track standard cell circuits for reduced area are provided. In one aspect, a minimum track standard cell circuit employs a first high aspect ratio voltage rail disposed over a first one-half track and configured to provide a first voltage (e.g., VDD) to the minimum track standard cell circuit. A second high aspect ratio voltage rail is disposed over a second one-half track substantially parallel to the first high aspect ratio voltage rail. The second high aspect ratio voltage rail is configured to provide a second voltage less than the first voltage (e.g., VSS) to the minimum track standard cell circuit. The minimum track standard cell circuit employs multiple tracks disposed between the first and second one-half tracks. The number of tracks can be limited based on particular factors. Minimizing tracks reduces area compared to conventional standard cell circuits.


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