The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 29, 2018

Filed:

May. 26, 2016
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Kuo-Cheng Ching, Hsinchu County, TW;

Jiun-Jia Huang, Yunlin County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 21/8238 (2006.01); H01L 29/423 (2006.01); H01L 27/092 (2006.01); H01L 29/06 (2006.01); H01L 29/165 (2006.01); H01L 21/02 (2006.01); H01L 29/10 (2006.01); H01L 29/78 (2006.01); H01L 29/51 (2006.01); H01L 29/66 (2006.01); H01L 29/775 (2006.01); B82Y 10/00 (2011.01); B82Y 40/00 (2011.01); H01L 21/84 (2006.01); H01L 29/786 (2006.01); H01L 21/311 (2006.01); H01L 29/49 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823821 (2013.01); B82Y 10/00 (2013.01); B82Y 40/00 (2013.01); H01L 21/02233 (2013.01); H01L 21/02236 (2013.01); H01L 21/02238 (2013.01); H01L 21/02255 (2013.01); H01L 21/31105 (2013.01); H01L 21/82385 (2013.01); H01L 21/823431 (2013.01); H01L 21/823807 (2013.01); H01L 21/823878 (2013.01); H01L 21/84 (2013.01); H01L 27/092 (2013.01); H01L 27/0922 (2013.01); H01L 27/0924 (2013.01); H01L 29/0673 (2013.01); H01L 29/0692 (2013.01); H01L 29/1037 (2013.01); H01L 29/165 (2013.01); H01L 29/42376 (2013.01); H01L 29/42392 (2013.01); H01L 29/517 (2013.01); H01L 29/66439 (2013.01); H01L 29/775 (2013.01); H01L 29/7854 (2013.01); H01L 29/78696 (2013.01); H01L 29/495 (2013.01); H01L 29/4966 (2013.01);
Abstract

A method includes providing a substrate having a first gate region for a first device and a second gate region for a second device, the first and second gate regions having different channel lengths. The method further includes forming first and second fins in at least the first and second gate regions respectively, and forming first and second stacks of semiconductor layers over the first and second fins respectively. The method further includes performing an oxidation process to the first and second stacks, thereby forming first and second semiconductor wires in the first and second gate regions respectively. Each of the first and second semiconductor wires is wrapped by a semiconductor oxide layer. The first and second semiconductor wires have different cross-sectional geometries in a respective plane that is perpendicular to their respective longitudinal direction.


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