The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 29, 2018
Filed:
Jul. 11, 2016
International Business Machines Corporation, Armonk, NY (US);
Hsueh-Chung Chen, Cohoes, NY (US);
Cheng Chi, Jersey City, NJ (US);
Lin Hu, Cohoes, NY (US);
Kafai Lai, Poughkeepsie, NY (US);
Chi-Chun Liu, Altamont, NY (US);
Jed W. Pitera, Portola Valley, CA (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method for local pattern density control of a device layout used by graphoepitaxy directed self-assembly (DSA) processes includes importing a multi-layer semiconductor device design into an assist feature system and determining overlapping regions between two or more layers in the multi-layer semiconductor device design using at least one Boolean operation. A fill for assist features is generated to provide dimensional consistency of device features by employing the overlapping regions to provide placement of the assist features. An updated device layout is stored in a memory device.