The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 29, 2018
Filed:
Sep. 19, 2016
Applicant:
Infineon Technologies Ag, Neubiberg, DE;
Inventors:
Manfred Mengel, Bad Abbach, DE;
Joachim Mahler, Regensburg, DE;
Khalil Hosseini, Weihmichl, DE;
Franz-Peter Kalz, Regensburg, DE;
Assignee:
INFINEON TECHNOLOGIES AG, Neubiberg, DE;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/48 (2006.01); H01L 23/373 (2006.01); H01L 21/77 (2017.01); H01L 23/495 (2006.01); H01L 23/00 (2006.01); H01L 21/56 (2006.01); H01L 25/00 (2006.01);
U.S. Cl.
CPC ...
H01L 21/4807 (2013.01); H01L 21/4825 (2013.01); H01L 21/56 (2013.01); H01L 21/77 (2013.01); H01L 23/3731 (2013.01); H01L 23/3735 (2013.01); H01L 23/49562 (2013.01); H01L 23/49575 (2013.01); H01L 23/49586 (2013.01); H01L 24/27 (2013.01); H01L 24/743 (2013.01); H01L 25/50 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48145 (2013.01); H01L 2224/48247 (2013.01); H01L 2224/48465 (2013.01); H01L 2224/48472 (2013.01); H01L 2224/49111 (2013.01); H01L 2224/73265 (2013.01); H01L 2224/83192 (2013.01); H01L 2224/92247 (2013.01); H01L 2924/07802 (2013.01); H01L 2924/12032 (2013.01); H01L 2924/1301 (2013.01); H01L 2924/1305 (2013.01); H01L 2924/1306 (2013.01); H01L 2924/13034 (2013.01); H01L 2924/13091 (2013.01); H01L 2924/181 (2013.01);
Abstract
A chip arrangement is provided, the chip arrangement, including a carrier; a first chip electrically connected to the carrier; a ceramic layer disposed over the carrier; and a second chip disposed over the ceramic layer; wherein the ceramic layer has a porosity in the range from about 3% to about 70%.