The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 29, 2018

Filed:

Oct. 16, 2017
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Mark Debbage, Santa Clara, CA (US);

Yatin M. Mutha, Pune, IN;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/36 (2006.01); G06F 13/372 (2006.01); G06F 13/362 (2006.01); G06F 13/42 (2006.01); G06F 13/28 (2006.01); G06F 5/06 (2006.01); G06F 13/16 (2006.01); G06F 15/78 (2006.01);
U.S. Cl.
CPC ...
G06F 13/372 (2013.01); G06F 5/065 (2013.01); G06F 13/1673 (2013.01); G06F 13/28 (2013.01); G06F 13/3625 (2013.01); G06F 13/4221 (2013.01); G06F 13/4282 (2013.01); G06F 15/7807 (2013.01); G06F 2205/067 (2013.01); G06F 2213/0026 (2013.01); G06F 2213/2806 (2013.01);
Abstract

Method and apparatus for implementing an optimized credit return mechanism for packet sends. A Programmed Input/Output (PIO) send memory is partitioned into a plurality of send contexts, each comprising a memory buffer including a plurality of send blocks configured to store packet data. A storage scheme using FIFO semantics is implemented with each send block associated with a respective FIFO slot. In response to receiving packet data written to the send blocks and detecting the data in those send blocks has egressed from a send context, corresponding freed FIFO slots are detected, and a lowest slot for which credit return indicia has not be returned is determined. The highest slot in a sequence of freed slots from the lowest slot is then determined, and corresponding credit return indicia is returned. In one embodiment an absolute credit return count is implemented for each send context, with an associated absolute credit sent count tracked via software that writes to the PIO send memory, with the two absolute credit counts used for flow control.


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