The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 22, 2018

Filed:

May. 03, 2017
Applicant:

Innolux Corporation, Miao-Li County, TW;

Inventors:

Jung-Fang Chang, Miao-Li County, TW;

Chih-Hao Wu, Miao-Li County, TW;

Chao-Hsiang Wang, Miao-Li County, TW;

Yi-Ching Chen, Miao-Li County, TW;

Assignee:

INNOLUX CORPORATION, Miao-Li County, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/786 (2006.01); H01L 27/12 (2006.01); G02F 1/1362 (2006.01); G02F 1/1368 (2006.01); H01L 29/417 (2006.01); H01L 23/538 (2006.01); H01L 29/423 (2006.01); G02F 1/1345 (2006.01); G02F 1/1333 (2006.01); G02F 1/136 (2006.01); H01L 27/32 (2006.01);
U.S. Cl.
CPC ...
H01L 29/78696 (2013.01); G02F 1/1368 (2013.01); G02F 1/136277 (2013.01); G02F 1/136286 (2013.01); H01L 23/538 (2013.01); H01L 27/124 (2013.01); H01L 27/1222 (2013.01); H01L 27/1288 (2013.01); H01L 29/41733 (2013.01); H01L 29/42384 (2013.01); G02F 1/13452 (2013.01); G02F 2001/13606 (2013.01); G02F 2001/133388 (2013.01); G02F 2001/136236 (2013.01); H01L 27/3262 (2013.01); H01L 27/3276 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A display device is disclosed, which includes: a substrate; a first conductive layer disposed on the substrate and including a gate with a gate edge parallel to a first direction; a semiconductor layer disposed on the first conductive layer; and a second conductive layer disposed on the semiconductor layer and including a drain and a data line extending along the first direction, the second conductive layer electrically connecting to the semiconductor layer, the drain including a drain edge parallel to the first direction, the gate edge located between the data line and the drain edge, and a projection of the drain on the substrate located in a projection of the semiconductor layer on the substrate. Herein, a maximum width of the semiconductor layer overlapping the gate edge along the first direction is smaller than maximum widths thereof overlapping the gate and the drain edge along the first direction.


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