The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 22, 2018

Filed:

Nov. 16, 2015
Applicants:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

National Taiwan University, Taipei, TW;

Inventors:

Der-Chuan Lai, Taipei, TW;

Samuel C Pan, Hsinchu, TW;

Yu-Cheng Shen, Taipei, TW;

Min-Hung Lee, New Taipei, TW;

Chee-Wee Liu, Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 21/28 (2006.01); H01L 29/16 (2006.01); H01L 29/40 (2006.01); H01L 29/51 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/78391 (2014.09); H01L 21/28291 (2013.01); H01L 29/16 (2013.01); H01L 29/401 (2013.01); H01L 29/513 (2013.01); H01L 29/516 (2013.01); H01L 29/6684 (2013.01); H01L 29/7856 (2013.01);
Abstract

The present disclosure provides a semiconductor device in accordance with some embodiments. The semiconductor device includes a substrate; a gate stack over the substrate. The gate stack includes a ferroelectric layer; a first dielectric material layer; and a first conductive layer. One of the first dielectric material layer and the ferroelectric layer is electrically charged to form a charged layer with fixed charge. The semiconductor device further includes source and drain features formed on the substrate and disposed on sides of the gate stack.


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