The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 22, 2018

Filed:

Apr. 24, 2017
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Kyongsoon Cho, Incheon, KR;

Myoungkyun Kil, Seoul, KR;

Hansung Ryu, Seoul, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Suwon-si, Gyeonggi-Do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/02 (2006.01); H01L 23/22 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2006.01); H01L 23/48 (2006.01); H01L 25/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/562 (2013.01); H01L 23/481 (2013.01); H01L 25/0657 (2013.01); H01L 25/50 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06555 (2013.01); H01L 2225/06582 (2013.01);
Abstract

Disclosed are a semiconductor package and a method of fabricating the same. The semiconductor package includes a first substrate, and a first semiconductor chip positioned above the first substrate. A second semiconductor chip is positioned above a top surface of the first semiconductor chip. An adhesive layer is between the first semiconductor chip and the second semiconductor chip. A second substrate is disposed on the second semiconductor chip. The second substrate substantially covers a top surface of the second semiconductor chip. A mold layer is disposed between the first substrate and the second substrate.


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