The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 22, 2018

Filed:

Mar. 22, 2016
Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventors:

Tatsuo Nakayama, Hitachinaka, JP;

Hironobu Miyamoto, Hitachinaka, JP;

Assignee:

Renesas Electronics Corporation, Koutou-ku, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/10 (2006.01); H01L 29/207 (2006.01); H01L 29/34 (2006.01); H01L 29/66 (2006.01); H01L 29/778 (2006.01); H01L 29/78 (2006.01); H01L 21/768 (2006.01); H01L 29/423 (2006.01); H01L 29/417 (2006.01); H01L 29/45 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76898 (2013.01); H01L 29/1087 (2013.01); H01L 29/207 (2013.01); H01L 29/34 (2013.01); H01L 29/66446 (2013.01); H01L 29/66462 (2013.01); H01L 29/7786 (2013.01); H01L 29/78 (2013.01); H01L 29/41758 (2013.01); H01L 29/4236 (2013.01); H01L 29/452 (2013.01);
Abstract

Characteristics of a semiconductor device are improved. A semiconductor device includes a voltage clamp layer, a channel base layer, a channel layer, and a barrier layer on a substrate. A trench extends to a certain depth of the channel layer through the barrier layer. A gate electrode is disposed on a gate insulating film within the trench. A source electrode and a drain electrode are provided on the two respective sides of the gate electrode. A coupling within a through-hole that extends to the voltage clamp layer electrically couples the voltage clamp layer to the source electrode. An impurity region containing an impurity having an acceptor level deeper than that of a p-type impurity is provided under the through-hole. The voltage clamp layer decreases variations in characteristics such as threshold voltage and on resistance. The contact resistance is reduced through hopping conduction due to the impurity in the impurity region.


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