The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 22, 2018

Filed:

Dec. 03, 2015
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Mei-Hsuan Lin, Tainan, TW;

Chih-Hsun Lin, Tainan, TW;

Ching-Hua Chu, Kaohsiung, TW;

Ling-Sung Wang, Tainan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/28 (2006.01); H01L 21/285 (2006.01); H01L 29/417 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
H01L 21/28518 (2013.01); H01L 21/02381 (2013.01); H01L 21/02425 (2013.01); H01L 21/02532 (2013.01); H01L 21/02617 (2013.01); H01L 21/28052 (2013.01); H01L 21/28568 (2013.01); H01L 29/41783 (2013.01); H01L 29/4975 (2013.01); H01L 29/665 (2013.01); H01L 29/66507 (2013.01); H01L 29/7845 (2013.01); H01L 21/0262 (2013.01); H01L 21/02631 (2013.01); H01L 21/2855 (2013.01); H01L 21/28097 (2013.01); H01L 21/28556 (2013.01); H01L 29/4933 (2013.01); H01L 29/7848 (2013.01);
Abstract

A method of forming a semiconductor device includes forming a gate stack over a first portion of a source and a first portion of a drain. The method includes depositing a first cap layer comprising silicon over a second portion of the source and depositing a second cap layer comprising silicon over a second portion of the drain. The method includes depositing a metal layer over the gate stack, the first cap layer and the second cap layer. The method includes annealing the semiconductor device until all of the silicon in the first and second cap layers reacts with metal from the metal layer, wherein the annealing causes metal from the metal layer to react with silicon in the first cap layer, the second cap layer, the source, and the drain. Annealing the semiconductor device includes forming a salicide layer having a germanium concentration less than 3% by weight.


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