The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 22, 2018

Filed:

Dec. 15, 2016
Applicant:

Ostendo Technologies, Inc., Carlsbad, CA (US);

Inventors:

Gregory Batinica, San Diego, CA (US);

Kameshwar Yadavalli, Carlsbad, CA (US);

Qian Fan, Carlsbad, CA (US);

Benjamin A. Haskell, Carlsbad, CA (US);

Hussein S. El-Ghoroury, Carlsbad, CA (US);

Assignee:

Ostendo Technologies, Inc., Carlsbad, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/302 (2006.01); H01L 21/02 (2006.01); H01L 21/66 (2006.01); H01L 23/31 (2006.01); H01L 23/00 (2006.01); H01L 29/20 (2006.01); H01L 29/30 (2006.01);
U.S. Cl.
CPC ...
H01L 21/02035 (2013.01); H01L 21/02002 (2013.01); H01L 22/20 (2013.01); H01L 23/3171 (2013.01); H01L 24/94 (2013.01); H01L 29/2003 (2013.01); H01L 29/30 (2013.01); H01L 21/0217 (2013.01); H01L 21/02164 (2013.01); H01L 21/02172 (2013.01); H01L 21/02274 (2013.01); H01L 23/562 (2013.01); H01L 2224/94 (2013.01); H01L 2924/3511 (2013.01);
Abstract

A method to improve the planarity of a semiconductor wafer and an assembly made from the method. In a preferred embodiment of the method, a compressive PECVD oxide layer such as SiOhaving a predetermined thickness or pattern is deposited on the second surface of a semiconductor wafer having an undesirable warp or bow. The thickness or pattern of the deposited oxide layer is determined by the measured warp or bow of the semiconductor wafer. The compressive oxide layer induces an offsetting compressive force on the second surface of the semiconductor wafer to reduce the warp and bow across the major surface of the semiconductor wafer.


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