The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 22, 2018

Filed:

Nov. 15, 2013
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Raheel Khan, Tustin, CA (US);

Fahad Ali Mujahid, Irvine, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/30 (2018.01); G06F 7/76 (2006.01); G06F 15/80 (2006.01); G06F 9/38 (2018.01);
U.S. Cl.
CPC ...
G06F 9/30181 (2013.01); G06F 7/76 (2013.01); G06F 9/3001 (2013.01); G06F 9/30032 (2013.01); G06F 9/30036 (2013.01); G06F 9/3887 (2013.01); G06F 9/3897 (2013.01); G06F 15/8053 (2013.01);
Abstract

Vector processing engines (VPEs) employing reordering circuitry in data flow paths between execution units and vector data memory to provide in-flight reordering of output vector data stored to vector data memory are disclosed. Related vector processor systems and methods are also disclosed. Reordering circuitry is provided in data flow paths between execution units and vector data memory in the VPE. The reordering circuitry is configured to reorder output vector data sample sets from execution units as a result of performing vector processing operations in-flight while the output vector data sample sets are being provided over the data flow paths from the execution units to the vector data memory to be stored. In this manner, the output vector data sample sets are stored in the reordered format in the vector data memory without requiring additional post-processing steps, which may delay subsequent vector processing operations to be performed in the execution units.


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