The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 22, 2018

Filed:

Dec. 21, 2011
Applicants:

Ankush Varma, Hillsboro, OR (US);

Ian M. Steiner, Hillsboro, OR (US);

Krishnakanth V. Sistla, Beaverton, OR (US);

Matthew M. Bace, Andover, MA (US);

Vivek Garg, Folsom, CA (US);

Martin T. Rowland, Beaverton, OR (US);

Jeffrey S. Wilder, Olympia, WA (US);

Inventors:

Ankush Varma, Hillsboro, OR (US);

Ian M. Steiner, Hillsboro, OR (US);

Krishnakanth V. Sistla, Beaverton, OR (US);

Matthew M. Bace, Andover, MA (US);

Vivek Garg, Folsom, CA (US);

Martin T. Rowland, Beaverton, OR (US);

Jeffrey S. Wilder, Olympia, WA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/32 (2006.01); G06F 13/38 (2006.01);
U.S. Cl.
CPC ...
G06F 1/324 (2013.01); G06F 13/382 (2013.01);
Abstract

An apparatus and method for managing a frequency of a computer processor. The apparatus includes a power control unit (PCU) to manage power in a computer processor. The PCU includes a data collection module to obtain transaction rate data from a plurality of communication ports in the computer processor and a frequency control logic module coupled to the data collection module, the frequency control logic to calculate a minimum processor interconnect frequency for the plurality of communication ports to handle traffic without significant added latency and to override the processor interconnect frequency to meet the calculated minimum processor interconnect frequency.


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