The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 15, 2018

Filed:

Aug. 11, 2016
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Ralf Richter, Radebeul, DE;

Peter Krottenthaler, Dresden, DE;

Martin Mazur, Pulsnitz, DE;

Assignee:

GLOBALFOUNDRIES Inc., Grand Cayman, KY;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/115 (2017.01); H01L 27/11546 (2017.01); H01L 27/12 (2006.01); H01L 27/11521 (2017.01); H01L 29/78 (2006.01); H01L 29/788 (2006.01); H01L 29/423 (2006.01); H01L 29/161 (2006.01); H01L 29/10 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11546 (2013.01); H01L 27/11521 (2013.01); H01L 27/1207 (2013.01); H01L 29/1054 (2013.01); H01L 29/161 (2013.01); H01L 29/42328 (2013.01); H01L 29/7838 (2013.01); H01L 29/7881 (2013.01);
Abstract

A method of manufacturing a semiconductor device is provided including providing a silicon-on-insulator (SOI) substrate comprising a semiconductor bulk substrate, a buried insulation layer formed on the semiconductor bulk substrate and a semiconductor layer formed on the buried insulation layer, forming a first transistor device on and in the SOI substrate in a logic area of the SOI substrate, removing the semiconductor layer and the buried insulation layer from a memory area of the SOI substrate, forming a dielectric layer on the exposed semiconductor bulk substrate, forming a floating gate layer on the first dielectric layer, forming an insulating layer on the floating gate layer and forming a control gate layer on the insulating layer, wherein an upper surface of the floating gate layer is substantially at the same height level as an upper surface of the semiconductor layer remaining in the logic area.


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