The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 15, 2018
Filed:
Jan. 27, 2016
Applicant:
United Microelectronics Corp., Hsinchu, TW;
Inventors:
Hui Yang, Singapore, SG;
Chow-Yee Lim, Singapore, SG;
Assignee:
United Microelectronics Corp., Hsinchu, TW;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/788 (2006.01); H01L 27/11534 (2017.01); H01L 27/11521 (2017.01); H01L 27/11568 (2017.01); H01L 27/11573 (2017.01); H01L 29/51 (2006.01); H01L 29/45 (2006.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11534 (2013.01); H01L 21/0217 (2013.01); H01L 21/02164 (2013.01); H01L 27/11521 (2013.01); H01L 27/11568 (2013.01); H01L 27/11573 (2013.01); H01L 29/45 (2013.01); H01L 29/513 (2013.01); H01L 29/518 (2013.01);
Abstract
A semiconductor device including a logic transistor, a non-volatile memory (NVM) cell and a contact etching stop layer (CESL) is shown. The CESL includes a first silicon nitride layer on the logic transistor but not on the NVM cell, a silicon oxide layer on the first silicon nitride layer and on the NVM cell, and a second silicon nitride layer disposed on the silicon oxide layer over the logic transistor and disposed on the silicon oxide layer on the NVM cell.