The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 15, 2018

Filed:

Dec. 17, 2014
Applicant:

Mitsubishi Electric Corporation, Tokyo, JP;

Inventors:

Hideki Haruguchi, Tokyo, JP;

Yoshifumi Tomomatsu, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/739 (2006.01); H01L 29/08 (2006.01); H01L 27/07 (2006.01); H01L 29/423 (2006.01); H01L 29/10 (2006.01); H01L 29/861 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0716 (2013.01); H01L 29/0834 (2013.01); H01L 29/1004 (2013.01); H01L 29/1095 (2013.01); H01L 29/4238 (2013.01); H01L 29/7395 (2013.01); H01L 29/861 (2013.01);
Abstract

An IGBT includes an n-type drift layer, a p-type base layer and an n-type emitter layer formed on an upper surface of the n-type drift layer, and a p-type collector layer on a lower surface of the n-type drift layer. A FWD includes the n-type drift layer, a p-type anode layer formed on the upper surface of the n-type drift layer and an n-type cathode layer formed on the lower surface of the n-type drift layer. A p-type well is formed on the upper surface of the n-type drift layer in a wiring region and a termination region. A wiring is formed on the p-type well in the wiring region. The p-type well has a higher impurity concentration and is deeper than the p-type anode layer. The p-type well is not formed directly above the n-type cathode layer and is separate from a region directly above the n-type cathode layer.


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