The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 15, 2018

Filed:

Nov. 08, 2016
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Yonghwan Kwon, Suwon-si, KR;

Seung-Kwan Ryu, Seongnam-si, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Suwon-si, Gyeonggi-Do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 21/3105 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01); H01L 23/538 (2006.01);
U.S. Cl.
CPC ...
H01L 23/562 (2013.01); H01L 21/31058 (2013.01); H01L 21/565 (2013.01); H01L 23/3121 (2013.01); H01L 23/5386 (2013.01); H01L 23/5389 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 24/96 (2013.01); H01L 24/97 (2013.01); H01L 21/568 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/29147 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/73267 (2013.01); H01L 2224/92244 (2013.01); H01L 2224/94 (2013.01); H01L 2224/97 (2013.01); H01L 2924/18162 (2013.01); H01L 2924/3511 (2013.01); H01L 2924/3512 (2013.01); H01L 2924/37001 (2013.01);
Abstract

A semiconductor package includes a stack structure, a mold layer disposed on at least one sidewall of the stack structure, a redistribution line electrically connected to the stack structure, and an external terminal electrically connected to the redistribution line. The stack structure includes a semiconductor chip having an active surface and a non-active surface opposite to the active surface. A dummy substrate is disposed on the non-active surface of the semiconductor chip. An adhesive layer is disposed between the dummy substrate and the semiconductor chip. The mold layer includes a top surface adjacent to the redistribution line and a bottom surface opposite to the top surface. The dummy substrate is exposed through the bottom surface of the mold layer.


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