The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 15, 2018

Filed:

Mar. 31, 2017
Applicant:

Stmicroelectronics S.r.l., Agrate Brianza, IT;

Inventors:

Antonino Conte, Tremestieri Etneo, IT;

Carmelo Paolino, Palermo, IT;

Maurizio Francesco Perroni, Furnari, IT;

Salvatore Polizzi, Palermo, IT;

Assignee:

STMicroelectronics S.r.l., Agrate Brianza (MB), IT;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/12 (2006.01); H03K 19/0185 (2006.01); G11C 16/20 (2006.01); G11C 16/08 (2006.01); G11C 13/00 (2006.01); G11C 16/26 (2006.01);
U.S. Cl.
CPC ...
G11C 16/12 (2013.01); G11C 13/0004 (2013.01); G11C 16/08 (2013.01); G11C 16/20 (2013.01); G11C 16/26 (2013.01); H03K 19/018521 (2013.01);
Abstract

A level shifter circuit is designed to shift an input signal that switches within a first voltage range to supply an output signal that switches within a second voltage range, higher than the first voltage range. A first inverter stage has an input receiving the input signal and also has an output. A first capacitive element is connected between the output of the first input inverter stage and a first holding node. A latch stage is connected between the first holding node and a second holding node that is coupled to an output terminal, on which the output signal is present. The first input inverter stage is designed to operate in the first voltage range, and the latch stage is designed to operate in the second voltage range.


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