The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 08, 2018

Filed:

Aug. 16, 2016
Applicant:

United Microelectronics Corp., Hsinchu, TW;

Inventors:

Chia-Wen Wang, Tainan, TW;

Hsiang-Chen Lee, Kaohsiung, TW;

Wen-Peng Hsu, New Taipei, TW;

Kuo-Lung Li, Yunlin County, TW;

Meng-Chun Chen, Kaohsiung, TW;

Zi-Jun Liu, Kaohsiung, TW;

Ping-Chia Shih, Tainan, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/115 (2017.01); H01L 27/1157 (2017.01); H01L 29/792 (2006.01); H01L 29/78 (2006.01); H01L 27/11573 (2017.01); H01L 29/66 (2006.01); H01L 21/28 (2006.01); H01L 27/11543 (2017.01); H01L 27/11563 (2017.01);
U.S. Cl.
CPC ...
H01L 27/1157 (2013.01); H01L 21/28282 (2013.01); H01L 27/11543 (2013.01); H01L 27/11563 (2013.01); H01L 27/11573 (2013.01); H01L 29/6659 (2013.01); H01L 29/66833 (2013.01); H01L 29/7833 (2013.01); H01L 29/792 (2013.01);
Abstract

A method for fabricating a semiconductor structure is shown. A first gate of a first device and a second gate of a second device are formed over a semiconductor substrate. First LDD regions are formed in the substrate beside the first gate using the first gate as a mask. A conformal layer is formed covering the first gate, the second gate and the substrate, wherein the conformal layer has sidewall portions on sidewalls of the second gate. Second LDD regions are formed in the substrate beside the second gate using the second gate and the sidewall portions of the conformal layer as a mask.


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