The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 08, 2018

Filed:

Jan. 18, 2017
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Mirco Cantoro, Suwon-si, KR;

YeonCheol Heo, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/092 (2006.01); H01L 21/02 (2006.01); H01L 21/8258 (2006.01); H01L 21/306 (2006.01); H01L 29/267 (2006.01); H01L 29/06 (2006.01); H01L 27/11 (2006.01); H01L 21/762 (2006.01); H01L 21/8238 (2006.01); H01L 27/02 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0924 (2013.01); H01L 21/02532 (2013.01); H01L 21/02538 (2013.01); H01L 21/30604 (2013.01); H01L 21/76224 (2013.01); H01L 21/8258 (2013.01); H01L 21/823821 (2013.01); H01L 21/823828 (2013.01); H01L 21/823878 (2013.01); H01L 27/0207 (2013.01); H01L 27/1104 (2013.01); H01L 27/1116 (2013.01); H01L 29/0649 (2013.01); H01L 29/267 (2013.01); H01L 29/6656 (2013.01); H01L 29/66545 (2013.01); H01L 29/7848 (2013.01);
Abstract

A semiconductor device includes a substrate with an NMOSFET region and a PMOSFET region, a first active pattern on the NMOSFET region, a second active pattern on the PMOSFET region, a dummy pattern between the NMOSFET and PMOSFET regions, and device isolation patterns on the substrate that fill trenches between the first active pattern, the second active pattern, and the dummy pattern. Upper portions of the first and second active patterns have a fin-shaped structure protruding between the device isolation patterns. The upper portions of the first and second active patterns contain semiconductor materials, respectively, that are different from each other, and an upper portion of the dummy pattern contains an insulating material.


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