The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 08, 2018

Filed:

Nov. 08, 2016
Applicants:

Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai, CN;

Semiconductor Manufacturing International (Beijing) Corporation, Beijing, CN;

Inventors:

Shuai Zhang, Shanghai, CN;

Bo Hong, Shanghai, CN;

Jui Lin Lu, Shanghai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/266 (2006.01); H01L 29/66 (2006.01); H01L 21/762 (2006.01); H01L 21/265 (2006.01); H01L 21/308 (2006.01); H01L 21/311 (2006.01); H01L 21/3115 (2006.01); H01L 21/32 (2006.01);
U.S. Cl.
CPC ...
H01L 21/266 (2013.01); H01L 21/26513 (2013.01); H01L 21/76235 (2013.01); H01L 29/66553 (2013.01); H01L 21/3081 (2013.01); H01L 21/31111 (2013.01); H01L 21/31155 (2013.01); H01L 21/32 (2013.01);
Abstract

A method for manufacturing a semiconductor device includes providing a substrate structure including a substrate having multiple structures. Each of the structures includes an active region isolated by trenches in the substrate, an insulating layer on the active region, and a hardmask layer on the insulating layer. The method also includes performing a first ion implantation into a first structure configured to form a first type device, performing a pull-back process on the hardmask layer and on the insulating layer of the first structure to form a receded hardmask layer and a receded insulating layer and expose a corner portion of the active region, and performing a rounding process on the exposed corner portion. The rounded corner portion of the active region has an increased curvature radius that reduces the concentration of the electric field and improves the reliability of the semiconductor device.


Find Patent Forward Citations

Zhang, Shuai. (2018). Method of high voltage device fabrication (U.S. Patent No. 9966265). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9966265

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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