The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 08, 2018
Filed:
Feb. 08, 2017
Applicant:
Nxp Usa, Inc., Austin, TX (US);
Inventors:
Patrice M. Parris, Phoenix, AZ (US);
Weize Chen, Phoenix, AZ (US);
Richard J. De Souza, Chandler, AZ (US);
Md M. Hoque, Gilbert, AZ (US);
John M. McKenna, Chandler, AZ (US);
Assignee:
NXP USA, INC., Austin, TX (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01); G01N 27/414 (2006.01); H01L 29/788 (2006.01); H01L 49/02 (2006.01); H01L 21/28 (2006.01); G05F 1/575 (2006.01);
U.S. Cl.
CPC ...
G01N 27/4148 (2013.01); G05F 1/575 (2013.01); G11C 16/0416 (2013.01); H01L 21/28035 (2013.01); H01L 28/40 (2013.01); H01L 29/788 (2013.01);
Abstract
An ISFET includes a control gate coupled to a floating gate in a CMOS device. The control gate, for example, a poly-to-well capacitor, is configured to receive a bias voltage and effect movement of a trapped charge between the control gate and the floating gate. The threshold voltage of the ISFET can therefore by trimmed to a predetermined value, thereby storing the trim information (the amount of trapped charge in the floating gate) within the ISFET itself.