The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9961784 B1

Date of Patent:

May. 01, 2018

Filed:

Mar. 31, 2017

Manufacturing method of circuit substrate

Applicant:

Subtron Technology Co., Ltd., Hsinchu County, TW;

Inventor:

Tzu-Wei Huang, Hsinchu County, TW;

Assignee:

Subtron Technology Co., Ltd., Hsinchu County, TW;

Attorney:

JCIPRNET

Primary Examiner:

Livius R Cazan

Int. Cl.

CPC ...

H05K 3/46 (2006.01); H05K 3/42 (2006.01); H05K 3/00 (2006.01); H05K 3/02 (2006.01); H05K 1/11 (2006.01); B23K 11/11 (2006.01); B32B 37/02 (2006.01); B32B 37/04 (2006.01); B32B 38/10 (2006.01); B32B 38/04 (2006.01); B32B 37/00 (2006.01); B23K 101/42 (2006.01);

U.S. Cl.

CPC ...

H05K 3/4682 (2013.01); B23K 11/11 (2013.01); B32B 37/0084 (2013.01); B32B 37/02 (2013.01); B32B 37/04 (2013.01); B32B 38/04 (2013.01); B32B 38/10 (2013.01); H05K 1/115 (2013.01); H05K 3/0097 (2013.01); H05K 3/02 (2013.01); H05K 3/421 (2013.01); H05K 3/4652 (2013.01); B23K 2201/42 (2013.01); B32B 2307/202 (2013.01); B32B 2307/206 (2013.01); B32B 2311/12 (2013.01); B32B 2457/08 (2013.01); H05K 3/423 (2013.01); H05K 2201/09509 (2013.01); H05K 2201/09563 (2013.01); H05K 2203/1572 (2013.01); Y10T 29/49126 (2015.01); Y10T 29/49155 (2015.01); Y10T 29/49156 (2015.01); Y10T 29/49165 (2015.01);

Abstract

A manufacturing method of a circuit substrate includes the following steps. The peripheries of two metal layers are bonded to form a sealed area. Two insulating layers are formed on the two metal layers. Two including upper and bottom conductive layers are formed on the two insulating layers. Then, the two insulating layers and the two conductive layers are laminated so that the two metal layers bonded to each other are embedded between the two insulating layers. A part of the two insulating layers and a part of the two conductive layers are removed to form a plurality of blind holes exposing the two metal layers. A conductive material is formed in the blind holes and on the remained two conductive layers. The sealed area of the two metal layers is separated to form two separated circuit substrates.

Find Patent Forward Citations