The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 01, 2018

Filed:

Mar. 12, 2015
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Murat Kerem Akarvardar, Saratoga Springs, NY (US);

Jody A. Fronheiser, Delmar, NY (US);

Ajey Poovannummoottil Jacob, Watervliet, NY (US);

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 21/84 (2006.01); H01L 29/66 (2006.01); H01L 29/417 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66795 (2013.01); H01L 29/0649 (2013.01); H01L 29/41791 (2013.01); H01L 29/66545 (2013.01);
Abstract

Commonly fabricated FinFET type semiconductor devices with different (i.e., both taller and shorter) heights of an entirety of or only the channel region of some of the fins. Where only the channel of some of the fins has a different height, the sources and drains have a common height higher than those channels. The different fin heights are created by recessing some of the fins, and where only the channels have different heights, the difference is created by exposing a top surface of each channel intended to be shorter, the other channels being masked, and partially recessing the exposed channel(s). In both cases, the mask(s) may then be removed and conventional FinFET processing may proceed.


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