IDiyas

For the Inventor, By the Inventor

The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9960184 B1

PDFFull Text
Date of Patent:
May. 01, 2018

Filed:

Jul. 10, 2017

Fdsoi-capacitor

Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Jan Hoentschel, Dresden, DE;

Peter Baars, Dresden, DE;

Hans-Peter Moll, Dresden, DE;

Assignee:

GLOBALFOUNDRIES Inc., Grand Cayman, KY;

Attorney:

Amerson Law Firm, PLLC

Primary Examiner:

Mark Prenty

Int. Cl.
CPC ...
H01L 27/12 (2006.01); H01L 29/94 (2006.01); H01L 27/06 (2006.01); H01L 21/762 (2006.01); H01L 21/84 (2006.01); H01L 29/786 (2006.01); H01L 49/02 (2006.01); H01L 29/06 (2006.01); H01L 21/265 (2006.01); H01L 21/285 (2006.01); H01L 27/108 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1207 (2013.01); H01L 21/26513 (2013.01); H01L 21/28518 (2013.01); H01L 21/76264 (2013.01); H01L 21/84 (2013.01); H01L 27/0629 (2013.01); H01L 27/1087 (2013.01); H01L 27/10829 (2013.01); H01L 28/60 (2013.01); H01L 29/0649 (2013.01); H01L 29/786 (2013.01); H01L 29/94 (2013.01); H01L 27/1085 (2013.01);
Abstract

A semiconductor device includes a semiconductor-on-insulator (SOI) wafer having a semiconductor substrate, a buried insulating layer positioned above the semiconductor substrate, and a semiconductor layer positioned above the buried insulating layer. A shallow trench isolation (STI) structure is positioned in the SOI wafer and separates a first region of the SOI wafer from a second region of the SOI wafer, wherein the semiconductor layer is not present above the buried insulating layer in the first region, and wherein the buried insulating layer and the semiconductor layer are not present in at least a first portion of the second region adjacent to the STI structure. A dielectric layer is positioned above the buried insulating layer in the first region, and a conductive layer is positioned above the dielectric layer in the first region.

Find Patent Forward Citations

Loading…