The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 01, 2018

Filed:

May. 24, 2017
Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventor:

Hideki Makiyama, Tokyo, JP;

Assignee:

Renesas Electronics Corporation, Koutouo-ku, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/76 (2006.01); H01L 27/12 (2006.01); H01L 21/762 (2006.01); H01L 21/84 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1207 (2013.01); H01L 21/76283 (2013.01); H01L 21/84 (2013.01); H01L 29/0649 (2013.01);
Abstract

A method of manufacturing a semiconductor device including: preparing a substrate in which an insulating layer, a semiconductor layer, and an insulating film are laminated on a semiconductor substrate, and a device isolation region is embedded in a trench. The insulating film in a bulk region is removed; the semiconductor layer in the bulk region is removed; and thereafter the insulating film in the SOI region and the insulating layer in the bulk region are thinned. An impurity is implanted into the semiconductor substrate in the SOI region, and thereafter the insulating film in the SOI region and the insulating layer in the bulk region are removed.


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