The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 01, 2018

Filed:

Oct. 06, 2016
Applicant:

Alpha and Omega Semiconductor Incorporated, Sunnyvale, CA (US);

Inventor:

Yan Xun Xue, Los Gatos, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/535 (2006.01); H01L 21/768 (2006.01); H01L 21/78 (2006.01); H01L 23/498 (2006.01); H01L 21/48 (2006.01); H01L 23/31 (2006.01); H01L 23/00 (2006.01); H01L 23/48 (2006.01); H01L 21/304 (2006.01); H01L 21/56 (2006.01); H01L 25/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/535 (2013.01); H01L 21/304 (2013.01); H01L 21/486 (2013.01); H01L 21/4846 (2013.01); H01L 21/4853 (2013.01); H01L 21/561 (2013.01); H01L 21/76895 (2013.01); H01L 21/76898 (2013.01); H01L 21/78 (2013.01); H01L 23/3114 (2013.01); H01L 23/481 (2013.01); H01L 23/49811 (2013.01); H01L 23/49827 (2013.01); H01L 23/49844 (2013.01); H01L 23/49894 (2013.01); H01L 24/03 (2013.01); H01L 24/06 (2013.01); H01L 24/94 (2013.01); H01L 24/96 (2013.01); H01L 25/50 (2013.01); H01L 24/05 (2013.01); H01L 2224/034 (2013.01); H01L 2224/0361 (2013.01); H01L 2224/03622 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/05025 (2013.01); H01L 2224/0603 (2013.01); H01L 2224/06051 (2013.01); H01L 2224/13111 (2013.01); H01L 2224/94 (2013.01); H01L 2224/96 (2013.01); H01L 2924/12042 (2013.01); H01L 2924/13091 (2013.01);
Abstract

A method to provide a wafer level package with increasing contact pad area comprising the steps of forming a first packaging layer on wafer top surface, grinding the wafer back surface and etch through holes, depositing a metal to fill the through holes and covering wafer backside, cutting through the wafer from wafer backside forming a plurality of grooves separating each chip then depositing a second packaging layer filling the grooves and covering the wafer back metal, reducing the first packaging layer thickness to expose the second packaging layer filling the grooves and forming a plurality of contact pads overlaying the first packaging layer thereafter cutting through the second packaging layer in the grooves to form individual package.


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