The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 01, 2018

Filed:

Nov. 01, 2016
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Yi-Liang Ye, Kaohsiung, TW;

Kuang-Hsiu Chen, Tainan, TW;

Chun-Wei Yu, Tainan, TW;

Chueh-Yang Liu, Tainan, TW;

Wen-Jiun Shen, Yunlin County, TW;

Yu-Ren Wang, Tainan, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8238 (2006.01); H01L 29/161 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01); H01L 21/311 (2006.01); H01L 27/092 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823821 (2013.01); H01L 21/31116 (2013.01); H01L 21/823814 (2013.01); H01L 21/823864 (2013.01); H01L 27/0924 (2013.01); H01L 29/161 (2013.01); H01L 29/4916 (2013.01); H01L 29/6653 (2013.01);
Abstract

The present invention provides a method for forming a semiconductor device, comprising the following steps: firstly, a substrate is provided, having a NMOS region and a PMOS region defined thereon, next, a gate structure is formed on the substrate within the NMOS region, and a disposal spacer is formed on two sides of the gate structure, afterwards, a mask layer is formed on the PMOS region to expose the NMOS region, next, a recess is formed on two sides of the gate structure spaced from the gate structure by the disposal spacer within the NMOS region, the disposal spacer is then removed after the recess is formed, and an epitaxial layer is formed into the recess.


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