The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 01, 2018
Filed:
Dec. 13, 2011
Leena K. Puthiyedath, Beaverton, OR (US);
Raj K. Ramanujan, Federal Way, WA (US);
Michael Rothman, Puyallup, WA (US);
Blaise Fanning, Folsom, CA (US);
Vincent J. Zimmer, Federal Way, WA (US);
Leena K. Puthiyedath, Beaverton, OR (US);
Raj K. Ramanujan, Federal Way, WA (US);
Michael Rothman, Puyallup, WA (US);
Blaise Fanning, Folsom, CA (US);
Vincent J. Zimmer, Federal Way, WA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A non-volatile random access memory (NVRAM) is used in a computer system to provide instant responses to sleep state transitions. The computer system includes a processor coupled to an NVRAM, which is accessible by the processor without passing through an I/O subsystem. The NVRAM is byte-rewritable and byte-erasable by the processor. In response to a request to enter a powered sleep state, the computer system converts the powered sleep state into a powered-off sleep state with system memory context stored in the NVRAM. The powered sleep state is defined as a state in which power is supplied to volatile random access memory in the computer system, and the powered-off sleep state is defined as a state in which power is removed from the volatile random access memory. In response to a wake event, the computer system resumes working state operations using the system memory context stored in the NVRAM.