The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 01, 2018

Filed:

Dec. 02, 2016
Applicant:

Synopsys, Inc., Mountain View, CA (US);

Inventors:

Ngai Ngai William Hung, San Jose, CA (US);

Dhiraj Goswami, Wilsonville, OR (US);

Assignee:

Synopsys, Inc., Mountain View, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/10 (2006.01); G06F 1/24 (2006.01); G11C 7/22 (2006.01); G06F 13/10 (2006.01); G06F 13/12 (2006.01); G06F 11/30 (2006.01);
U.S. Cl.
CPC ...
G06F 1/24 (2013.01); G06F 11/3037 (2013.01); G06F 11/3055 (2013.01); G06F 13/105 (2013.01); G06F 13/124 (2013.01); G11C 7/1012 (2013.01); G11C 7/22 (2013.01);
Abstract

Disclosed is a resettable memory device including a memory unit, a reset status indicator circuit, a logic sampling circuit, and a multiplexer for performing a reset function. The memory unit includes cells for storing states of signals in a design under test. The reset status indicator stores states of indicators indicating whether corresponding cells should be reset or not. Responsive to the reset status indicator indicating that the value of the cell should not be reset, the multiplexer receives the value stored in the cell and outputs the retrieved value from the cell. Responsive to the reset status indicator indicating that the value of the cell should be reset, the multiplexer outputs a reset value instead of the value stored in the cell. The reset value may be changed by the logic sampling circuit at different time periods or certain logic conditions, and output through the multiplexer.


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