The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 24, 2018
Filed:
Mar. 30, 2016
Intel Corporation, Santa Clara, CA (US);
Raul Enriquez Shibayama, Zapopan, MX;
Karen Navarro Castillo, Tlaquepaque, MX;
Casey G Thielen, Gilbert, AZ (US);
Alfredo Cueva Gonzalez, Zapopan, MX;
Benjamin Lopez Garcia, Puebla, MX;
INTEL CORPORATION, Santa Clara, CA (US);
Abstract
Techniques and mechanisms for providing connectivity to an integrated circuit device via a hardware interface. In an embodiment, the hardware interface includes contacts forming an array of nodes. Some or all such nodes are arranged in cells, wherein the respective node types of each cell's nodes are according to the same cell pattern. The cell pattern includes eight B nodes for the exchange of data bits, four strobe S nodes for the exchange of strobe signals, and ground (G) nodes for the providing of one or more reference potentials. The cell pattern enables formation of a lattice structure including node-contiguous G nodes each of a respective one of the multiple cells. In another embodiment, a ratio of bi-level nodes (including all S nodes and all G nodes) of the cell pattern to a total number of G nodes of the cell pattern is 12:8 or more.