The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 24, 2018

Filed:

Sep. 25, 2015
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:
Assignee:

Infineon Technologies AG, Neubiberg, DE (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/423 (2006.01); H01L 21/02 (2006.01); H01L 29/78 (2006.01); H01L 29/739 (2006.01); H01L 21/308 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/4236 (2013.01); H01L 21/02244 (2013.01); H01L 21/3086 (2013.01); H01L 29/6656 (2013.01); H01L 29/66348 (2013.01); H01L 29/66719 (2013.01); H01L 29/66727 (2013.01); H01L 29/66734 (2013.01); H01L 29/7397 (2013.01); H01L 29/7813 (2013.01); H01L 29/42376 (2013.01);
Abstract

A method of forming a transistor having a gate electrode includes forming a sacrificial layer over a semiconductor substrate, forming a patterning layer over the sacrificial layer, patterning the patterning layer to form patterned structures, forming spacers adjacent to sidewalls of the patterned structures, removing the patterned structures, etching through the sacrificial layer using the spacers as an etching mask and etching into the semiconductor substrate, thereby forming trenches in the semiconductor substrate, and filling a conductive material in the trenches in the semiconductor substrate to form the gate electrode.


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