The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 24, 2018

Filed:

Feb. 03, 2017
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Kwan-Jae Song, Seoul, KR;

Jae-Hyun Yoo, Suwon-si, KR;

In-Hack Lee, Suwon-si, KR;

Seong-Hun Jang, Suwon-si, KR;

Myoung-Kyu Park, Yongin-si, KR;

Young-Mok Kim, Suwon-si, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Suwon-si, Gyeonggi-Do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 29/06 (2006.01); H01L 21/266 (2006.01); H01L 21/308 (2006.01); H01L 21/762 (2006.01); H01L 29/10 (2006.01); H01L 29/78 (2006.01); H01L 29/165 (2006.01); H01L 29/08 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0649 (2013.01); H01L 21/266 (2013.01); H01L 21/308 (2013.01); H01L 21/7624 (2013.01); H01L 29/1033 (2013.01); H01L 29/1083 (2013.01); H01L 29/165 (2013.01); H01L 29/7833 (2013.01); H01L 29/0847 (2013.01);
Abstract

A semiconductor device having a high and stable operating voltage and a method of manufacturing the same, the semiconductor device including: a substrate having an active region including a channel region; a gate insulating layer that covers a top surface of the active region; a gate electrode that covers the gate insulating layer on the top surface of the active region; buried insulating patterns in the channel region of the active region at a lower side of the gate electrode and spaced apart from a top surface of the substrate; and a pair of source/drain regions in the substrate at both sides of each of the buried insulating patterns and extending from the top surface of the substrate to a level lower than that of each of the buried insulating patterns.


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