The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 24, 2018

Filed:

Feb. 10, 2016
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Hongmei Li, Williston, VT (US);

Junjun Li, Cupertino, CA (US);

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); H01L 21/8234 (2006.01); H01L 27/088 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1211 (2013.01); H01L 21/823431 (2013.01); H01L 27/0886 (2013.01); H01L 29/0649 (2013.01); H01L 29/66795 (2013.01); H01L 29/7853 (2013.01);
Abstract

Aspects of the disclosure provide a multi-gate field effect transistor (FET) formed on a bulk substrate that includes an isolated fin and methods of forming the same. In one embodiment, the multi-gate FET includes: a plurality of silicon fin structures formed on the bulk substrate, each silicon fin structure including a body region, a source region, and a drain region; wherein a bottom portion the body region of each silicon fin structure includes a tipped shape to isolate the body region from the bulk substrate, and wherein the plurality of silicon fin structures are attached to the bulk substrate via at least a portion of the source region, or at least a portion of the drain region, or both.


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