The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 24, 2018
Filed:
Aug. 01, 2017
Applicant:
Synopsys, Inc., Mountain View, CA (US);
Inventors:
Assignee:
Synopsys, Inc., Mountain View, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/112 (2006.01); H01L 23/525 (2006.01); H01L 23/528 (2006.01); H01L 29/78 (2006.01); H01L 23/522 (2006.01); H01L 29/66 (2006.01); H01L 21/28 (2006.01); H01L 21/768 (2006.01); G06F 17/50 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11206 (2013.01); G06F 17/5068 (2013.01); H01L 21/28008 (2013.01); H01L 21/76895 (2013.01); H01L 23/5226 (2013.01); H01L 23/5252 (2013.01); H01L 23/5283 (2013.01); H01L 29/0649 (2013.01); H01L 29/66795 (2013.01); H01L 29/7851 (2013.01);
Abstract
Embodiments relate to an anti-fuse device with a transistor. The transistor may be a FinFET. The anti-fuse device includes a first electrode, an insulating layer, and a second electrode. The gate of the transistor may be formed in a same layer as the first electrode. The gate insulating layer on the gate of the transistor may be formed in a same layer as the insulating layer. The second electrode may be formed in a same layer as a local interconnect or a via and overlap the first electrode vertically over the insulating layer.