The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 24, 2018

Filed:

Mar. 25, 2014
Applicant:

Mitsubishi Materials Corporation, Tokyo, JP;

Inventors:

Toyo Ohashi, Kitamoto, JP;

Yoshiyuki Nagatomo, Saitama, JP;

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); B23K 35/26 (2006.01); C22C 13/00 (2006.01); H01L 23/373 (2006.01); H01L 23/473 (2006.01); H01L 23/488 (2006.01); B23K 35/28 (2006.01); B23K 35/02 (2006.01);
U.S. Cl.
CPC ...
H01L 24/29 (2013.01); B23K 35/0222 (2013.01); B23K 35/0238 (2013.01); B23K 35/26 (2013.01); B23K 35/262 (2013.01); B23K 35/28 (2013.01); B23K 35/286 (2013.01); C22C 13/00 (2013.01); H01L 23/3735 (2013.01); H01L 23/473 (2013.01); H01L 23/488 (2013.01); H01L 2224/29082 (2013.01); H01L 2224/29111 (2013.01); H01L 2224/29147 (2013.01); H01L 2224/32225 (2013.01); H01L 2924/13055 (2013.01); H01L 2924/3512 (2013.01);
Abstract

A power module is disclosed, including a power module substrate in which a circuit layer is arranged on one surface of an insulating layer; and a semiconductor element that is bonded onto the circuit layer, in which a copper layer composed of copper or a copper alloy is provided on a surface of the circuit layer to be bonded to the semiconductor element, a solder layer formed by using a solder material between the circuit layer and the semiconductor element is provided, an alloy layer containing Sn as a main component, 0.5% by mass or more and 10% by mass or less of Ni, and 30% by mass or more and 40% by mass or less of Cu at an interface of the solder layer with the circuit layer is formed, and the coverage of the alloy layer at the interface is 85% or more.


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