The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 24, 2018

Filed:

Jun. 09, 2014
Applicant:

Mitsubishi Electric Corporation, Tokyo, JP;

Inventors:

Masanori Nimura, Tokyo, JP;

Shigenori Takeda, Tokyo, JP;

Yoshinao Tatei, Tokyo, JP;

Ikio Sugiura, Tokyo, JP;

Assignee:

Mitsubishi Electric Corporation, Chiyoda-ku, Tokyo, JP;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/48 (2006.01); H01L 23/13 (2006.01); H01L 23/498 (2006.01); H01L 21/288 (2006.01); H01L 23/055 (2006.01); H01L 23/08 (2006.01);
U.S. Cl.
CPC ...
H01L 21/4817 (2013.01); H01L 21/288 (2013.01); H01L 21/4803 (2013.01); H01L 21/486 (2013.01); H01L 21/4857 (2013.01); H01L 23/055 (2013.01); H01L 23/08 (2013.01); H01L 23/13 (2013.01); H01L 23/49805 (2013.01); H01L 23/49822 (2013.01); H01L 23/49827 (2013.01); H01L 2924/0002 (2013.01);
Abstract

When a plating layer is formed on through holes in semiconductor packages, first and second stacked bodies are stacked with first and second cavities formed in the first and second stacked bodies facing the inner side and are bonded together by applying adhesive to peripheral regions so that the cavities of the first and second stacked bodies form sealed spaces, and the through holes are formed such that part of the first and second stacked bodies including the bonding surface remains. Then, the through holes are plated to form the plating layer, the peripheral regions are removed as cutting allowances, i.e., removal regions, and the first and second stacked bodies are divided into a plurality of pieces along dicing lines to form semiconductor packages.


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