The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 24, 2018

Filed:

Dec. 30, 2016
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Ye-Sin Ryu, Seoul, KR;

Sang-Uhn Cha, Yongin-si, KR;

Hoi-Ju Chung, Yongin-si, KR;

Seong-Jin Cho, Hwaseong-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/44 (2006.01); G11C 29/56 (2006.01); G11B 20/18 (2006.01); G01R 31/3187 (2006.01); G06F 11/27 (2006.01); G06F 11/10 (2006.01); G11C 29/52 (2006.01); G11C 5/04 (2006.01); G11C 11/40 (2006.01); G11C 17/16 (2006.01); G11C 17/18 (2006.01); G11C 29/02 (2006.01); G11C 29/00 (2006.01);
U.S. Cl.
CPC ...
G11C 29/44 (2013.01); G01R 31/3187 (2013.01); G06F 11/1068 (2013.01); G06F 11/27 (2013.01); G11B 20/1816 (2013.01); G11C 5/04 (2013.01); G11C 11/40 (2013.01); G11C 17/16 (2013.01); G11C 17/18 (2013.01); G11C 29/027 (2013.01); G11C 29/4401 (2013.01); G11C 29/52 (2013.01); G11C 29/56008 (2013.01); G11C 29/785 (2013.01); G11C 29/787 (2013.01); G11C 29/56004 (2013.01); G11C 2029/4402 (2013.01); G11C 2029/5606 (2013.01);
Abstract

A method of operating a semiconductor memory device is provided. In a method of operating a semiconductor memory device including a memory cell array which includes a plurality of bank arrays, memory cells in a first region of the memory cell array are tested to detect one or more failed cells in the first region, a fail address corresponding to the detected one or more failed cells is determined and the determined fail address is stored in a second region different from the first region, in the memory cell array.


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