The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 24, 2018
Filed:
Mar. 09, 2017
Toshiba Memory Corporation, Minato-ku, Tokyo, JP;
Sanad Bushnaq, Yokohama Kanagawa, JP;
Manabu Sato, Chigasaki Kanagawa, JP;
Toshiba Memory Corporation, Tokyo, JP;
Abstract
According to one embodiment, A level shifter includes a first circuit configured to generate a first signal, the first signal being inverted and delayed signal of a second signal, a NAND circuit including a first input terminal and a second input terminal, the second signal being input to the first terminal, the first signal being input to the second terminal, a first transistor, a first voltage being applied to a first terminal of the first transistor, a second terminal of the first transistor being connected to a third input terminal of the NAND circuit, a third signal which inverts the second signal being applied to a gate of the first transistor, a second transistor, a second voltage being applied to a first terminal of the second transistor, the second voltage being higher than the first signal, a gate of the second transistor being connected to an output terminal, a third transistor, the second voltage being applied to a first terminal of the third transistor, a second terminal of the third transistor being connected to a second terminal of the second transistor, the second signal being applied to a gate of the third transistor, and a fourth transistor, a first terminal of the fourth transistor being connected to the second terminal of the third transistor, a second terminal of the fourth transistor being connected to the output terminal, an output terminal of the NAND circuit being connected to a gate of the fourth transistor.