The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 24, 2018

Filed:

Jun. 06, 2016
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Bruce Querbach, Hillsboro, OR (US);

Kuljit S. Bains, Olympia, WA (US);

John B. Halbert, Beaverton, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G11C 11/406 (2006.01); G06F 3/06 (2006.01); G11C 14/00 (2006.01);
U.S. Cl.
CPC ...
G11C 11/40618 (2013.01); G06F 3/0604 (2013.01); G06F 3/0632 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G11C 14/0009 (2013.01);
Abstract

A memory subsystem enables a refresh abort command. A memory controller can issue an abort for an in-process refresh command sent to a memory device. The refresh abort enables the memory controller to more precisely control the timing of operations executed by memory devices in the case where a refresh command causes refresh of multiple rows of memory. The memory controller can issue a refresh command during active operation of the memory device, which is active operation refresh as opposed to self-refresh when the memory device controls refreshing. The memory controller can then issue a refresh abort during the refresh, and prior to completion of the refresh. The memory controller thus has deterministic control over both the start of refresh as well as when the memory device can be made available for access.


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