The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 24, 2018
Filed:
Oct. 21, 2016
Applicant:
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Inventors:
John J. Wuu, Ft. Collins, CO (US);
Ryan Freese, Ft. Collins, CO (US);
Russell J. Schreiber, Austin, TX (US);
Assignee:
Advanced Micro Devices, Inc., Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/41 (2006.01); G11C 11/419 (2006.01); G11C 7/12 (2006.01); H03K 19/0185 (2006.01); G11C 7/06 (2006.01); G11C 7/22 (2006.01);
U.S. Cl.
CPC ...
G11C 7/12 (2013.01); G11C 7/06 (2013.01); G11C 7/22 (2013.01); H03K 19/018507 (2013.01);
Abstract
An interlock circuit utilizes a single combinatorial pseudo-dynamic logic gate to take inputs from two voltage domains at the same time without requiring either input to be level shifted. The interlock design allows hold timing to be met across a large voltage range of both supplies in a dual-voltage supply environment while not significantly hurting setup time by having much lower latency than the latency of a level shifter.